electiveHQ

This module deals with the design of digital systems, starting from the required behaviour and working towards a circuit. Students should already be familiar with combinational logic circuits and the basics of sequential logic. The emphasis will be on design at register transfer level (RTL). A hardware description language (Verilog) will be used to describe a design in a way that can be understood by synthesis software. Verification of the behaviour of a design will also be covered, using testbenches and simulation software. Laboratory work will involve design assignments and the use of the relevant software tools, with implementation on FPGA. These assignments will require significant effort during the trimester, and this is an important part of the learning process. You cannot learn to design digital systems by cramming for an exam!